Conventionally, a NAND flash memory in which data can be electrically rewritten utilizes metal-oxide-semiconductor (MOS) transistors each having a stacked gate structure formed by stacking a charge accumulation layer (ex. floating gate) and control gate as nonvolatile memory elements (flash memory cells). For example, the data write operation is performed by injecting electrons into the floating gate to change the threshold voltage (Vth) of the MOS transistor. The data read operation is performed by sensing a cell current that varies according to a variation in the threshold voltage of the MOS transistor, that is, injection/non-injection of electrons into the floating gate by a sense amplifier.
In the above NAND flash memory, the flash memory cell is increasingly miniaturized. Therefore, an attempt is made to miniaturize the chip or increase the memory capacity of each chip. However, an influence of each atom becomes significant with miniaturization of the flash memory cell and there occurs a problem that a variation in the threshold value becomes larger due to fluctuation of impurities.
As a method for reducing fluctuation of the impurities, a method for lowering (thinning) the impurity concentration of a substrate surface that becomes an inversion layer of a channel portion in a metal-insulator-semiconductor field effect transistor (MISFET) is already proposed. Such a proposal is disclosed in Jpn. Pat. Appln. KOKAI Publications No. H11-40764 and No. H11-145304, for example.
However, if the impurity concentration of the channel portion is lowered, the source region and drain region of the MISFET tend to be electrically connected. Particularly, since the distance between the source region and drain region becomes smaller (shorter) if miniaturization is further advanced, they tend to be electrically connected more easily. If the source region and drain region between the flash memory cells are electrically connected, the MISFET cannot function as a flash memory cell.
Further, the structure of a MISFET in which source regions and drain regions are not formed is also proposed. Such a proposal is disclosed in Japanese Patent No. 3,522,836, for example. However, with this structure, it is necessary to provide a conductive layer between gate electrodes of adjacent MISFETs.